Field of the Disclosure
The present disclosure relates to a through wiring substrate, a device that includes the through wiring substrate, a method of producing the through wiring substrate, a method of producing the device, and so forth.
Description of the Related Art
For reduction of the sizes of devices and advancement of the functions of the devices such as an increase in speed and an increase in the number of functions, through wirings are used. The through wirings allow chips included in such a device to be electrically connected to one another or elements on the top surface of a substrate to be electrically connected to wiring on the bottom surface of the substrate with smallest distances. The through wirings may be formed by a via-first method or a via-last method. With the via-first method, the through wirings are formed before the elements are formed. With the via-last method, the through wirings are formed after the elements have been formed. With the via-first method, a high-quality insulating film can be deposited at a high temperature on the surface of the substrate including inner walls of through holes. This is suitable for a device which needs to have a high dielectric strength. However, when a temperature increasing step is required for the formation of an element structure, it is required to consider effects on the elements due to heat diffusion to the substrate that is the material for forming the through wirings and the difference in thermal expansion between the through wirings and the substrate.
In order to reduce the heat diffusion, a barrier layer may be provided. In order to reduce the difference in thermal expansion, the through wirings can be formed of a material which is similar to the material of the substrate. For example, when the substrate is formed of silicon, the wirings may be formed of phosphorus-doped polysilicon. However, the through wirings formed of polysilicon have a drawback of having a high resistivity. Thus, the through wirings can be formed of metal in the case where the element structure can be formed at a comparatively low temperature. For example, the substrate is formed of silicon and the through wirings are formed of Cu. In this case, the thermal expansion coefficient of Cu is six times larger than that of silicon. Accordingly, when the temperature increases and decreases to form the elements, the through wirings contract and expand or slide relative to the inner wall of the through hole. Due to such a movement, end surfaces of the through wirings project from the surface of the substrate when the temperature increases. This may cause a thin film included in each element to be, for example, deformed, permanently deformed, or to be damaged. Furthermore, when the temperature decreases, such a wiring attempts to return to its original state and draws the thin film. This may cause, in the proximity of the end surface, the thin film to be permanently deformed, damaged, or stress in the thin film may increase. Such permanent deformation of the thin film, damage to the thin film, an increase in stress in the thin film, and so force may cause deficiency of the element and variation of the performance among the elements. In order to reliably obtain the performance of the element, it is possible that the element is not disposed near the through wiring. In this case, however, the degree of integration of elements reduces. In order to reduce or suppress permanent deformation of the thin film, damage to the thin film, or the increase in stress in the thin film, it is required that a relative movement of the through wiring due to a change in temperature be suppressed on the substrate surface side where the element is disposed.
Japanese Patent Laid-Open No. 2013-165100 discloses a technique in which scallops (surface irregularities) is formed in an inner wall of a through hole and the width and depth of the scallops are controlled. When the through wiring is formed in the through hole having such scallops, a structure in which the surface of the through wiring and the inner wall of the through hole are engaged with each other can be produced. Accordingly, the relative movement of the through wiring to the substrate due to the change in temperature can be suppressed.
However, the technique of Japanese Patent Laid-Open No. 2013-165100 has been developed for forming an insulating film and other thin films uniformly on the inner wall of the through hole with a good adhesion property through a via-last method, and the scallops are formed entirely in the through hole. Furthermore, the scallops are formed such that the width and depth of the scallops are smaller on the surface side where the element is disposed than on the surface side where no element is disposed. When the scallops are formed entirely in the through hole, the through wiring is engaged with the inner wall throughout the entire length of the through, and accordingly, restrained. Thus, when the temperature increases or decreases, the through wiring has large stress between the through wiring and the inner wall of the through hole. Due to this stress, the scallops and the thin film formed on the scallops may be eternally deformed or damaged, and accordingly, desired functions are not necessarily performed. Furthermore, the width and depth of the scallops are comparatively small on the surface side where the element is disposed, and accordingly, a force to restrain the through wiring is comparatively small. Thus, the relative movement of the through wiring due to the increase and decrease in temperature may be concentrated on the surface side where the element is disposed. This may increase the effects on the thin film and the like included in the element.